Design and Implementation of Low Leakage Power SRAM System Using Full Stack Asymmetric SRAM
|Rajlaxmi Belavadi1, Pramod Kumar.T1, Obaleppa. R. Dasar2, Narmada. S2, Rajani. H. P3
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This paper explores the design and analysis of Static random Access Memory (SRAMs), focusing on optimizing delay and power. To address sub threshold leakage issue full stack approach is used. The full stack technique reduces leakage power to a great extent. The full stack technique is applied to SRAM cell in asymmetric manner in order to realise still higher power reduction. This work compares performance of SRAM using full stack approach with that of conventional 6T-SRAM design. The impact of temperature and different process corners on the performance of full stack design is also analysed. The static power and dynamic power measurement is done using Cadence Virtuoso ADE Visualization and Analysis XL Browser and XL Calculator. The layout is drawn and verified for DRC, LVS and RC extraction using Cadence Assura Tool.