Design and Implementation of Reduced Area and Low Power SQRT CSLA and its Application in ALU
In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate level modification is used in order to reduce the area, delay and power of CSLA. In this paper 16 –bit square root carry select adders are designed and compared. Based on the modifications, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. Implement conventional CSLA, BEC-based CSLA, CBL-based CSLA and Area-delay-power efficient are compared with proposed SQRT CSLA in terms of area, delay and power consumption. The result analysis shows that the proposed structure is better than the existing CSLAs. Also an arithmetic logic unit is designed using the proposed CSLA. The proposed carry select adder and arithmetic logic unit is designed by using VHDL and is implemented in spartan 3E FPGA.