Design and Power Optimization of MTCMOS circuits using Power Gating Techniques
|Velicheti Swetha1, S Rajeswari2
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Now-a-days Power consumption (or) power dissipation has becomes the most important criteria for implementing anyone of the digital circuit. While calculating the efficient value of the output of that particular digital circuit, we may use the concept of scaling. But, while increasing the scaling process there may be a loss of leakage current. Due to the leakage current the usage of power (power dissipation) is increased. For removing these kinds of leakage currents we are going to use “power gating techniques”. By using the power gating techniques we can provide better power efficiency also. In this paper we are going to analyze the digital circuits using different types of power gated circuits with the help of low power VLSI design techniques. By using the nanometer technology we may get different results for different digital power gating circuits. The entire procedure may implement and simulated using Micro-wind Layout Editor & D. Sch (Digital Schematic).