alexa DESIGN OF HIGH SPEED HARDWARE EFFICIENT 4-BIT SFQ MULT
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

DESIGN OF HIGH SPEED HARDWARE EFFICIENT 4-BIT SFQ MULTIPLIER

K. Ramesh1, M.Vaidehi2
  1. Asst. Professor, Dept. of ECE, St.Anne’s CET, Anna University, Chennai, India
  2. Asst. Professor, Dept. of ECE, St.Anne’s CET, Anna University, Chennai, India
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Abstract

A 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) is designed. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method. The proposed 4-bit modified booth encoders are designed using Quartus II. The area, delay and power performance of the booth encoder and modified Booth Encoder have been evaluated from the simulated output analysis shows that modified Booth encoder implemented SFQ multiplier better compared to conventional booth encoder.

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