alexa Design of Low Power Non Volatile Magnetic Flip-Flop or Memories Based on Lector Technique
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
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Research Article

Design of Low Power Non Volatile Magnetic Flip-Flop or Memories Based on Lector Technique

D.shilpa1, S.Senthurpriya2
  1. PG Scholar, Department of ECE, Muthayammal Engineering College, Namakkal, India
  2. Assistant Professor, Department of ECE, Muthayammal Engineering College, Namakkal, India
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Abstract

Power has becoming a burning issue in modern VLSI design. Non volatile memories like MRAM, FeRAM , ReRAM etc can save power by allowing the system power off in standby state. MRAM can be built up by using Magnetic Flip-flop like portable computer, Floppy disk, CD's etc. Comparing to the conventional Flip-flop STTMRAM can save the power and retain the data by using 22 nm technology .Advanced computing systems suffer from high static power due to rapidly rising leakage currents in deep sub-micron MOS technologies. In this paper performed electrical simulations to validate its functional behaviors and evaluate its performance by using spice model of STTMRAM. Some mechanisms like checkpointing/power gating has been undergone in this NVM(non-volatile memories). There are numerous methods proposed to control leakage power dissipation. LECTOR is one of the techniques used for leakage reduction without affecting the dynamic power. The proposed design requires less design effort and offers greater power reduction and smaller area cost than the previous method. in leakage power reduction when compared to all other existing leakage reduction techniques. Using this LECTOR technique, power efficiency becomes better. This paper presents the analysis for leakage current in Static RAM implementing LECTOR technique

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