alexa Efficient Hardware Design for Implementation of Matrix
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

Efficient Hardware Design for Implementation of Matrix Multiplication by using PPI-SO

Shivangi Tiwari1 and Nitin Meena2
  1. Dept. of EC, IES College of Technology, Bhopal, India
  2. Assistant Professor, Dept. of EC, IES College of Technology, Bhopal, India
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In this paper, we have proposed one designs for matrix-matrix multiplication. The one design differs by hardware complexity, throughput rate and different input/output data format to match different application needs. We have compared the proposed designs with the existing similar design and found that, the proposed designs offer higher throughput rate at relatively lower hardware cost. We have synthesized the proposed design and the existing design using Synopsys tools. Synthesis results shows that proposed design on average consumes nearly 30% less energy than the existing design and involves nearly 70% less area-delay-product than other. Interestingly, the proposed parallel-parallel input and single output (PPI-SO) structure consumes 40% less energy than the existing structure.


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