alexa Energy Efficient Design for Full Adder Logic Implement
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

Energy Efficient Design for Full Adder Logic Implementation

Rakhi Saha, Sambita Dalal, Satyasis Mishra
  1. M.Tech. Scholar, Dept. of E.C.E., SoET, Centurion University, Jatani, Odisha, India.
  2. Assistant Professor, Dept. of E.C.E., SoET, Centurion University, Jatani, Odisha, India
  3. Associate Professor, Dept. of E.C.E., SoET, Centurion University, Jatani, Odisha, India.
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Abstract

In VLSI applications, area, delay and power are the important factors which must be taken into account which can be minimized by using Reversible logic design. The reversible logic gates are now finding profound as well as promising applications in emerging growing paradigms such as Quantum computing, Quantum Dot Cellular Automata, Optical Computing, Digital Signal Processing, Nanotechnology and etc. This paper presents the novel designs of full adder by using improved reversible logic gates. The main purpose of designing using reversible circuit is to decrease the number of garbage outputs and the number of gates and transistor used.

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