Flip-Flop Grouping in Data-Driven Clock Gating for Dynamic Power Management
|N.Indhumathi1 and Dr.S.Nirmala2
|Related article at Pubmed, Scholar Google|
Data driven clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Power optimization plays the important role in the recent years. Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation.Gating manually inserted into the register transfer level (RTL) design. when a logic unit is clock, its underlying sequential elements receive the clock signal regardless of whether or not they will toggle in the next cycle. In this flip-flops are grouped so that they share a common clock enabling signal to reduce the hardware overhead. It is observed that the commonly used synthesis based gating still leaves a large amount of redundant clock pulses. In these d-flip flops are used to grouping for reducing the power. Here the Xilinx software tool will be used for implementing this proposal system.