HIGH SPEED LOW POWER EMBEDDED DRAM DESIGN FOR DIGITAL APPLICATIONS
A.Lakshminarayanan and S.Ganesan
Assistant Professor, Dept. of ECE, Kongunadu College of Engineering and Technology,Thottiam, Tamilnadu, India
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In this paper a fully synchronous circuit for embedded DRAMs is presented. It realizes accurate DRAM timing control, and easy timing adjustment, power dissipation analysis for 3T DRAM cell and 4T DRAM cell design have been carried out for the Nanoscale technology. Many advanced processors now have on chip instructions and data memory using DRAMs. The major contribution of power dissipation in DRAM cell is off-state leakage current. Thus, improving the power efficiency of a DRAM cell is critical to the overall system power dissipation. This paper investigates the effectiveness of 3T DRAM cell and 4T DRAM cell circuit design techniques and power dissipation analysis. 3T DRAM cell is designed with the semantic design technique for the analysis of power dissipation using CADENCE Tool. In this paper, we have taken two circuits of dynamic random access memory (DRAM). Read and write operation for single bit storage of 3T DRAM and 4T DRAM circuit is shown by simulating it on Tanner EDA tool.