HIGH SPEED PARALLEL CONCURRENT ERROR DETECTION SCHEME FOR ROBUST AES HARDWARE
Amandeep Kamboj1, R. K Bansal2 and Savina Bansal2
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This paper proposes the high speed parallel concurrent error detection scheme for robust AES hardware. Very large scale integration devices are very susceptible to transient errors. Due to the efficiency and flexibility of the advanced encryption standard (AES) algorithm, it becomes the popular choice in different applications like embedded systems; satellites etc. AES is the current standard for the secret key encryption. The FIPS 197 used a standardized version of the algorithm called as Rijndael for AES. This paper basically shows the detection of soft error in the AES cipher output during the hardware implementations.The hardware design of this AES block with single bit error correction was accomplished using VHDL and implemented on Xilinx Virtex 6 FPGA. The modelling process utilized in this project is the bottom-up approach. All the modules in the design hierarchy were modelled in behavioural style, but the root module consisted of data flow modelling. This process yields better results as hardware is developed in such a fashion that it supports parallelism in it.