alexa Implementation of Galois Field Arithmetic Unit on FPGA
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
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Research Article

Implementation of Galois Field Arithmetic Unit on FPGA

1LakhendraKumar, 2Dr. K. L. Sudha
  1. B.E project scholar, VIII SEM, Dept. of E&C, DSCE, Bangalore, India
  2. Professor, Dept. of E&C, DSCE, Bangalore, India
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Abstract

Finite Field arithmetic is becoming increasingly a very prominent solution for calculations in many applications. Galois Field arithmetic forms the basis of BCH, Reed-Solomon and other erasure coding techniques to protect storage systems from failures. Most implementations of Galois Field arithmetic rely on multiplication tables or discrete logarithms to perform this operation. Software-based Galois field implementations are used in the reliability and security components of many storage systems. Unfortunately, multiplication and division operations over Galois fields are expensive, compared to the addition. To accelerate multiplication and division, most software Galois field implementations use pre-computed look-up tables, accepting the memory overhead associated with optimizing these operations. However, the amount of available memory constrains the size of a Galois field and leads to inconsistent performance across architectures. Typical arithmetic unit includes an adder or subtracter, multiplier and divider. Addition operation is done with one n-bit XOR operation, for multiplication operation LSB first multiplying method is used and Fermat’s little theorem for multiplicative inverse operation. These operations are implemented on FPGA Virtex v.5 kit & simulated using Verilog on Xilinx 14.2 ISim simulator. Arithmetic unit architecture is measuredin terms of %age of device utilized and time delay.

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