alexa Implementation of High Speed Low Power Split-SAR ADCs
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

Implementation of High Speed Low Power Split-SAR ADCs

M. Ranjithkumar 1, C.Selvi2, M.Bhuvaneswaran 3
  1. PG Scholar, Department of Electronics and Communication Engineering, Muthayammal Engineering College, Namakkal, India
  2. Assistant Professor, Department of Electronics and Communication Engineering, Muthayammal Engineering College, Namakkal, India
  3. Assistant professor, Department of Electronics and Communication Engineering, Muthayammal Engineering College, Namakkal, India
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Abstract

This paper analyzes the parasitic effects in SAR ADCs. Which achieves a significant switching energy saving when compared with set-and-down and charge-recycling switching approaches. Successive approximation technique in ADC is well known logic, where in the presented design the linearity analysis of a Successive Approximation Registers (SAR) Analog-to-Digital Converter (ADC) with split DAC structure based on two switching methods: VCM -based switching, Switch to switchback process. The main motivation is to implement design of capacitor array DAC and achieve high speed with medium resolution using 45nm technology. The current SAR architecture has in built sample and hold circuit, so there is significant saving in chip area. The other advantage is matching of capacitor can be achieved better then resistor. Which is verified by behavioural Measurement results of power, speed, resolution, and linearity clearly show the benefits of using VCM-based switching? In the proposed design the SAR ADC is designed in switch to switchback process such a way that the control module completely control the splitting up of modules, and we planning to give an option to change the speed of operation using low level input bits. A dedicated multiplexer is designed for that purpose system.

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