alexa Implementation of Image Processing Algorithm Using Partial Dynamic Reconfiguration in FPGA
ISSN ONLINE(2319-8753)PRINT(2347-6710)

International Journal of Innovative Research in Science, Engineering and Technology
Open Access

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Special Issue Article

Implementation of Image Processing Algorithm Using Partial Dynamic Reconfiguration in FPGA

 
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Abstract

High Performance Reconfigurable Computing (HPRC) is parallel computing systems that contain multiple Microprocessors and multiple FPGAs. In current settings, the design uses FPGAs as coprocessors that are deployed to execute the small portion of the application that takes most of the time, under the 10-90 rules, the 10 percent of code that takes 90 percent of the execution time. FPGAs can certainly accomplish this when computations lend themselves to implementation in hardware, subject to the limitations of the current FPGA chip architectures and the overall system data transfer constraints. Hardware reconfigurable devices that change their configurations under the control of a program can replace the FPGAs to satisfy the same key concepts behind this class of architectures. Hence FPGAs are the currently available technology that provides the most desirable level of hardware reconfigurability. This paper focuses on Image enhancement and Denoising process, reference to point processing methods such as brightness manipulation, threshold operation and median filtering operation in FPGA with Onboard reconfiguration and partial dynamic reconfiguration. When using a partial dynamic reconfiguration performance of FPGA increases and the resource requirement decreases.

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