alexa Implementation of Low Power All Digital Phase Locked Loop
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
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Research Article

Implementation of Low Power All Digital Phase Locked Loop

Rajani Kanta Sutar1, M.Jasmin2 and S. Beulah Hemalatha3
  1. PG Scholar, Bharath University, Tamilnadu, India
  2. Assistant Professor, Department of ECE, Bharath University, Tamilnadu, India
  3. Assistant Professor, Department of ECE, Bharath University, Tamilnadu, India
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Abstract

Phase locked loop is a familiar circuit for high frequency application and very short interlocking time. In this paper we have implemented and analysed All Digital Phase locked loop (ADPLL), as the present applications requires a low cost, low power and high speed Phase locked loops. The design is synthesized in Xilinx ISE software. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. This project gives details of the basic blocks of an ADPLL. In this project it is been planned to implementation of ADPLL. Its simulation results are verified for all the corners of inputs. The ADPLL is planned for 200 MHz central frequency

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