alexa Parallel AES Encryption Engines for Many-Core Processo
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Special Issue Article

Parallel AES Encryption Engines for Many-Core Processor Arrays

H. Naveen, M. Ramesh
  1. Graduate Student, Department Of ECE, Indus College Of Engineering, Coimbatore, India
  2. Assistant Professor, Department Of ECE, Indus College Of Engineering, Coimbatore, India
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Abstract

By exploring different granularities of data-level and task-level parallelism, we map 4 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained manycore system. The smallest design utilizes only six cores for offline key expansion and eight cores for online key expansion, while the largest requires 107 and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Most AES calculations are done in a special field. The AES cipher is specified as a number of repetitions of transformation rounds that convert the input plain-text into the final output of cipher-text. Each round consists of several processing steps, including one that depends on the encryption key. A set of reverse rounds are applied to transform cipher-text back into the original plain-text using the same encryption key.

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