Performance Improvement of Low Power Double Tail Comparator in UDSM CMOS Technology
|1N.Bhuvaneswari, 2V.Gowrishankar, 3Dr.K.Venkatachalam
In this paper, we present a performance comparison of dynamic comparators. As delay is directly correlated with the submicron scaling, we investigate the performance of the above comparators in terms of delay and Power-Delay Product (PDP). PDP gives the average energy dissipated by the comparator for a single comparison. Simulation results using Tanner EDA revealed better performance of High Speed Dynamic Comparator (HSDC) compared to conventional clocked comparators in 180nm, 250nm and 350nm technologies. Implementation results reveal that high speed dynamic comparator has energy dissipation compared to the best of the designs used for comparison in 180nm technology, when operated at 50 MHz.