Power and Area Minimization of Reconfigurable FFT Processor using Distributed ArithmeticAnuradha M* and Vishal R
Electronics & Telecommunication Engineering Department, SavitribaiPhule, Pune University, India
- *Corresponding Author:
- Anuradha M
Electronics & Telecommunication Engineering Department
SavitribaiPhule, Pune University, India.
E-mail: [email protected]
Received date: 12/12/2015; Accepted date: 19/03/2016; Published date: 28/04/2016
Fast Fourier transforms is one of the most important frequency analysis in signal processing. It has different application such as image processing, medical field, communication system, spectral analysis etc. Butterfly is the basic elements of FFT. In this work a Distributed arithmetic technique is used to implement the butterfly module. Distributed arithmetic is Multiplierless technique resulted more efficient butterfly element both in terms of power and area. Butterfly element is the most important building block of Reconfigurable FFT processor. Single precision is used to represent the data. IEEE 754 standard is used to represent the floating point numbers.