Ultra-Low Power Design of Digital CMOS Logic Circuits
|M.Valarmathi1, Siddharth Bhat2, Shubham Choudhary3
|Related article at Pubmed, Scholar Google|
Power and area are the two major concerns in design of any digital circuit. At present scenario low power device design and its implementation have got a significant role in the field of nano electronics. However much research not has been done at ultra-low power with acceptable performance and high performance design with power. To achieve the ultra-low power requirement is to operate the digital logic gates in subthreshold region. This paper investigates the analysis of CMOS technology in 45 nm channel length where the relative study of average power dissipation of CMOS inverter. We analyze and compare CMOS Inverter and other logic gates in subthreshold region. The subthreshold current is found to be exponentially related to the gate voltage. Thus,this exponential relationship not only gives an exponential reduction in power consumption, but also an exponential increase in delay. The simulation results are taken at 45nm using CMOS technology with the help of Cadence tool. The simulation results show that the reduction in power outweighs the increase in propogation delay.