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Research Article Open Access
A low power 2GHz PLL frequency synthesizer for Zigbee/IEEE 802.15.4 applications is presented. The current starve VCO is used to decrease power consumption and to improve noise characteristic of the synthesizer. The Synthesizer employs a 1 MHz fully programmable divider with an improved TSPC 2/3 prescaler, a novel bit-cell for the programmable counters and PFD,charge pump and passive loop filter to reduce the PLL reference spurs. The PLL consumes a power of 1.026mW at 1 V power supply with the programmable divider consuming only 613.39 μW. The phase noise of the VCO is – 44.77dBc/Hz at 1 MHz offset.Measured results show that the frequency tuning range is 2.46GHz-2.541GHz and the locking time is 4μs. The synthesizer is design and simulated on Tanner EDA Tool using 45nm CMOS process technology with supply voltage 1 V.