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Research Article Open Access
The research community in the last few years from the field of approximate computing has received significant attention, particularly in the context of different signal processing. Image and video compression algorithms such as JPEG, MPEG and so on, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximations statically and are not adaptive to input data. This project addresses this issue by proposing a reconfigurable approximate for MPEG encoders that optimizes power consumption with the aim of maintaining a particular peak signal-to-noise ratio threshold for any video. I design reconfigurable adder/sub tractor blocks, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. I propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the characteristics of each individual video. Dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound PSNR degradation across different videos while power saving a dual mode full adder is greater than the full adder, when compared to existing implementations.
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Author(s): J.Jayakodi, K.Sagadevan
Approximate circuits, low power design, approximate computing, quality configurable, Electronic Materials, Optical Communication, Electric Drivers and Application.