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Research Article Open Access
This project survey review on optimization of CIC filter, and as architecture aspects of up sampling and down sampling rate using CIC filter and comparison between the results in hardware and simulations. Processing a high data rate signal is a difficult task. Reducing the data rate of such signals would ease the processing significantly. In a communications system, two systems might be working at different a rate which requires a rate change process. This is achieved by the use of a decimator or an interpolator. Here CIC filter on designing models are developed for using Xilinx system generator, by cascading various CIC filter stages. The hardware is synthesized in FPGA and verified with Model sim and Mat lab simulation results. This project also discusses about performance analysis with respect to the number of stages (N) and rate change factor (R) of the filter pipelining, throughput and area reduction techniques.