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Research Article Open Access
Carry Select Adder (CSLA) which provides one of the fastest adding performance. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work uses a simple and efficient gate-level modification Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- mμ CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. The proposed design has been developed using verilog HDL. synthesized and simulated using Xilinx ISE Simulator and verification is done using modelsim.