alexa A Novel Approach in Pipeline Architecture for 64-Point
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Special Issue Article

A Novel Approach in Pipeline Architecture for 64-Point FFT Processor without ROM

A.Manimaran1, Dr.S.K.Sudheer2 and Manu.K.Harshan3
  1. Associate Professor, Department of ECE, Karpaga Vinayaga College of Engineering and Technology Chennai, India
  2. Assistant professor, Department of ECE, University of Kerala, India
  3. M.E. Embedded System Technologies, Department of ECE, Karpaga Vinayaga College of Engineering and Technology , Chennai, India
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FFT processor is an important unit in modern wireless communication system. So more research and developments take place in this field. The paper reports low power efficient implementation of FFT processor. Proposed architecture in the design is single-path delay feedback (SDF) pipeline architecture. The requirement of memory and utilization of multipliers is comparatively less in this architecture so that this architecture is very efficient for low power and smaller area FFT designs that is mainly using in portable DSP devices. Proposed architecture completely eliminates the use of ROM by using a reconfigurable complex multiplier and bit-parallel multipliers. Symmetric property of twiddle factor is also used in the proposed multiplier to get low power.

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