ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
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Research Article


U. Soma Naidu1 and K.Venkateswarlu2
  1. M.Tech Student, Dept. of ECE, Prakasam Engineering College, Kandukur, Prakasam (dt), A.P, India
  2. Associate professor, Dept. of ECE, Prakasam Engineering College, Kandukur, Prakasam (dt), A.P, India
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Power reduction has become a vital design goal for sophisticated design applications, whether mobile or not. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-flop method is to eliminate total inverter number by sharing the inverters in the flip-flops. Since the ring counter is made up of an array of D-type flip-flops (DFFs) triggered by a global clock signal it is possible to disable the clock signal to most DFFs. Such a gated-clock ring counter is implemented to compose a low-power first-in first-out (FIFO) memory. In this paper, we will review multi-bit flip-flop concepts, and introduce the benefits of using multi-bit flip-flops in our design. we proposed to use double-edge-triggered (DET) flipflops instead of traditional DFFs in the ring counter to halve the operating clock frequency. A novel approach using the C-elements instead of the R–S flip-flops in the control logic for generating the clock-gating signals is adopted to avoid increasing the loading of the global clock signal. The technique will greatly decrease the loading on distribution network of the clock signal for the ring counter and thus the overall power consumption. The same technique is applied to the input driver and output driver of the memory part in the delay buffer. Then, we will show how to implement multi-bit flip-flop methodology using gated drive tree by XILINX Design Compiler. Experimental results indicate that multi-bit flip-flop using gated drive tree is very effective and efficient method in lower-power designs.

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