alexa Accumulator Based 3-Weight Test Pattern Generation
ISSN ONLINE(2319-8753)PRINT(2347-6710)

International Journal of Innovative Research in Science, Engineering and Technology
Open Access

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Special Issue Article

Accumulator Based 3-Weight Test Pattern Generation

Geetanjali M. Dhurmekar, V.S. Dhongde
  1. PG Student [VLSI & Embedded Systems], Dept. of E&TC, University of Pune, Maharashtra, India
  2. Head of Dept., Dept. of E&TC, University of Pune, Maharashtra, India
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Abstract

Pseudorandom built-in self test (BIST) generators have been globally used to test integrated circuit and systems. In a BIST design, the generation, application of the test vectors and analysis of the resulting response are part of the system or circuit under test. Weighted pseudorandom BIST schemes have been utilized in order to minimize the number of vectors to achieve complete fault coverage in BIST applications. In accumulator based 3-weight test pattern generation scheme, weighted sets comprising 3 weights namely 0, 1 and 0.5 have been successfully utilized, since they result in both low consumed power and low testing time. The main advantages of this scheme over existing schemes are: 1) Only three easily generated weights-0, 1, 0.5 are used. 2) As accumulators are commonly used in current VLSI chips, this scheme can efficiently drive down the hardware of BIST pattern generation. 3) This scheme does not require any redesign of adder (i.e. it can be implemented using any adder design). 4) This scheme does not affect the operating speed of the adder. Comparisons between previously presented schemes show that the proposed scheme compares favorably with respect to the required hardware.

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