An FPGA for a Multibank Memory-Based VLSI Architecture of DVB symbol Deinterleaver
An efficient symbol-deinterleaver architecture compliant with the digital-video-broadcasting (DVB) standard is proposed. By partitioning the entire symbol buffer into four separate parts with a special low-conflict access control strategy, the symbol deinterleaver can be implemented with four-bank single-port on-chip memory blocks with slight overhead. By this we can save hardware cost very much compared with the conventional double-buffer approach. In addition, we can also use a look head online circuit of a symbol permutation-address generator, which provides required permutation addresses every cycle to avoid either the use of a lookup table or an extra temporary buffer. As the major part of the entire DVB forward-error-correction decoder, the proposed symbol deinterleaver can contribute a great saving of the overall decoder cost.