alexa Analysis of Different Bit Carry Lookahead Adder with R
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
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Research Article

Analysis of Different Bit Carry Lookahead Adder with Reconfigurability in Low Power VLSI Using Verilog Code

C. Suba1, S. Karthick2 and M. Prakash1
  1. PG Scholar, Department of ECE, Bannari Amman Institute of Technology, Erode, Tamil Nadu, India
  2. Assistant Professor, Department of ECE, Bannari Amman Institute of Technology, Erode, Tamil Nadu, India
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Fast addition plays an important role in advanced digital system. Recently, reconfigurable adders have been widely employed to achieve real time processing of media signals. This paper presents a design-forreconfigurability (DFR) technique for carry look ahead adders (CLAs)[1]. The various adder structures can be used to execute addition such as serial and parallel structures and most of researches have done research on the design of high-speed, low-area, or low- power adders. Adders like ripple carry adder, carry select adder, Shannon adder ,carry look ahead adder, carry skip adder, carry save adder [2] exist numerous adder implementations each with good attributes and some drawbacks. This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16- bit carry look-ahead adder based on Verilog code [3] and compared for their performance in Xilinx [1]. We have recorded the performance improvements in propagating the carry and generating the sum when compared with the traditional carry look ahead adder designed in the same technology [4] [5].


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