alexa Design and Implementation Boundary Scan Register for T
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
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Research Article

Design and Implementation Boundary Scan Register for Trace and Debug of Controller

Mr. Manjunath T.N1, Sunil T.D2, Dr. M. Z Kurian3, Imran Rasheed4
  1. PG Student [VLSI & Embedded systems], Sri Siddhartha Institute Of Technology, Tumkur, Karnataka, India
  2. Asst. Professor, Dept. of ECE Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
  3. HOD, Dept. of ECE, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
  4. Asst. Professor, Dept. of EEE, M.S.Ramaiah School of Advanced Studies, Bangalore, Karnataka, India
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The paper aims about the trace and debug of any N-bit controller using a JTAG, here controller core is traced using a interfacing device known as JTAG (Joint Test Action Group). JTAG is an advanced DFT Technique for the purpose of testing an ASIC, as such there are various technique for this purpose, but JTAG is chosen for its unique feature of in built state machine which can used for the purpose of both interfacing and display unit with a device as well as a testing device.


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