Design and Implementation of REA for Single Precision Floating Point Multiplier Using Reversible Logic
|MadivalappaTalakal1, G.Jyothi2, K.N.Muralidhara3, M.Z.Kurian4
|Related article at Pubmed, Scholar Google|
The IEEE 754 single precision floating point multiplier uses reversible exponent adder to accomplish multiplication operation. The REA is designed and implemented using reversible logic gates like Peres gate and TR gate. Reversible logic is used to reduce the power dissipation compared to classical logic and it can also reduces the information loss so which finds application in different fields like low power computing operations, quantum computing, optical computing techniques, and may also used in other emerging computing technologies. Verilog is used to implement a technology-independent pipelined design. The multiplier can be designed to handles the overflow and underflow cases. Implementation of rounding will not gives more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. In other (truncated) multiplication technique by truncation method rounding may also be implemented for further reduction in power dissipation and area. The entire design of reversible exponent addition using reversible ripple carry adder and reversible ripple borrow subtractor is modeled using Verilog hardware description language .The coding is done on Xilinx ISE 12.2 and simulation is performed on Modelsim 6.3.