alexa Design and Simulation of 64-Bit Carry Select Adder Usin
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

OMICS International organises 3000+ Global Conferenceseries Events every year across USA, Europe & Asia with support from 1000 more scientific Societies and Publishes 700+ Open Access Journals which contains over 50000 eminent personalities, reputed scientists as editorial board members.

Open Access Journals gaining more Readers and Citations

700 Journals and 15,000,000 Readers Each Journal is getting 25,000+ Readers

This Readership is 10 times more when compared to other Subscription Journals (Source: Google Analytics)

Research Article

Design and Simulation of 64-Bit Carry Select Adder Using Gate Level Architecture for Low Power Applications

 
To read the full article Peer-reviewed Article PDF image

Abstract

An efficient VLSI based system has a very high speed operation capability along with low power requirement for performing any operation. The modern systems are required to have very efficient hardware architecture in order to utilize the hardware efficiency to result in best performance. The increasing processor speed and data handling require a high speed circuit to perform the complex calculations. The basic processing operations include addition, multiplication, division, code conversion, encoding-decoding, encryption-decryption, mixing of signal, register-shift, etc. These operations are performed in combination to result in a complex operation. Addition is among the simplest operations. For a data with high length the time taken by the adder to generate output increases in proportion to the length of data. The present work presents the design and simulation of gate level circuit of a 64-bit carry select adder (CSLA) design. The design of CSLA and its simulation test-bench is written using VHDL language. This brief also presents an analysis based on the dynamic power consumption of the field programmable gate array (FPGA) devices in performing the addition operation using the presented design. Xilinx Tool is used in performing the design, simulation and synthesis of the present work.

Keywords

Share This Page

Additional Info

Loading
Loading Please wait..
Peer Reviewed Journals
 
Make the best use of Scientific Research and information from our 700 + peer reviewed, Open Access Journals
International Conferences 2017-18
 
Meet Inspiring Speakers and Experts at our 3000+ Global Annual Meetings

Contact Us

 
© 2008-2017 OMICS International - Open Access Publisher. Best viewed in Mozilla Firefox | Google Chrome | Above IE 7.0 version
adwords