Special Issue Article
Design of 2/3 prescalerLow Power Flexible Multiband Divider
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The demand for lower cost, lower power, and multiband RF circuits increased in conjunction with need of higher level of integration. In this project a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and Network standard’s 802.15.4 and 802.11 a/b/g Wireless LAN frequency synthesizers is proposed based on pulseswallow topology and is implemented. The frequency synthesizer, usually implemented by a phase-locked loop (PLL), is one of the power-hungry blocks in the RF front-end and the first-stage frequency divider consumes a large portion of power in a frequency synthesizer. The proposed prescaler based approach reduces the area and power significantly. The multiband divider consists of a proposed wideband multi modulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.41–2.483 GHz, 5.14–5.30 GHz, and 5.715–5.815 GHz with a resolution selectable from 1 to 25 MHz The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mw in 2.3-and 5-GHz bands, respectively, when operated at 1.8-V power supply. The proposed prescaler is achieved by without using any additional flip flops. It gives a solution to the low power PLL synthesizers for wide range of communication applications.