Special Issue Article
Design of ALU with LFSR Using Clock Gating
This paper proposes a method to reduce the power consumption of a 32 bit linear feedback shift register. The proposed scheme is based on data driven clock gating approach and it can offer improved power reduction based on the technological characteristics of the employed gates compared to the traditional gated design approach. Reduction of dynamic power is done by the effective management of utilization of clock signal for the flip flops present in the LFSR circuit by adopting the grouping of available flip flops .The dynamic power consumption due to unnecessary switching of the clock gated circuitry is eliminated by a modified approach in the design of clock gating circuitry. The LFSR designed so can be used in the design of an arithmetic and logic unit (ALU) with the designed LFSR as on of its input register and hence reduce the power consumption of the overall system. Further power saving is done by means of the application of power saving modes to the ALU circuit when the inputs are not subjected to change.