Design of Low voltage Comparator for Analog to Digital Conversion
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Comparators play a very important role in high speed analog to digital converters, to maximize speed and power efficiency. In this paper a clocked comparator has been used since can make fast decisions due to the strong positive feedback in the regenerative latch. The accuracy is given by its input referred offset voltage, essential for the resolution of high performance ADC’s. This is methods of reducing power and delay in dynamic latch comparator circuit over the double tail comparator and pre-amplifier based comparators. In order to reduce the circuit delay we are going to use double tail transistor, one at the top Vdd and other at the bottom Vss, by including this transistor positive feedback during regeneration is strengthened, which reduces delay time. In the proposed comparator, power consumption and delay are reduced significantly to 7.4ns and 12 μw respectively. Post-layout simulation results in 0.18-μm CMOS technology used for results analysis.