alexa Double Precision IEEE-754 Floating-Point Adder Design
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

Double Precision IEEE-754 Floating-Point Adder Design Based on FPGA

Adarsha KM1, Ashwini SS2 and Dr. MZ Kurian3
  1. PG Student [VLS& ES], Dept. of ECE, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
  2. Assistant professor, Dept. of ECE, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
  3. HOD, Dept. of ECE, Sri Siddhartha Institute of Technology, Tumkur, Karnataka, India
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Because of dynamic representation capabilities and large spectrum of numbers can be represented with limited number of bits, floating-point numbers are being widely adapted in the fields of scientific applications. A floating-point arithmetic unit is specifically designed to carry out on floating-point numbers and is one of the most common part of any computing system in the area of binary applications. Floating-point additions are the most frequent floating-point operations and floating-point adders are therefore critically important components in signal processing and embedded platforms. This review paper presents the survey of related works of different algorithms/techniques which are important for implementation of double precision floating point adder with reduced latency based on FPGAs. As per the review paper the basic design deals with the floating point adder implementation, the proposed design handles delay optimization.


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