alexa Efficient Multiplier-less Design for 1-D DWT Using 9/7
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
Open Access

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Research Article

Efficient Multiplier-less Design for 1-D DWT Using 9/7 Filter Based on NEDA Scheme

Jagdamb Behari Srivastava1, R.K. pandey2 and Jitendra Jain3
  1. Programme Asst. (Computer), Jawaharlal Nehru Krishi Vishwavidyalaya , Jabalpur, India
  2. Dr. , Prof. & Head, UICSA, Rani Durgavati Vishwavidyalaya , Jabalpur, India
  3. Assistant Professor, Dept. of ECE, JUET College of Engineering, Guna, India
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In this paper, we present a new efficient distributed arithmetic (NEDA) formulation of the computation of 1-D discrete wavelet transform (DWT) using 9/7 filters, and mapped that into bit parallel for high-speed and low hardware implementations, respectively. We demonstrate that NEDA is a very efficient architecture with adders as the main component and free of ROM, multiplication, and subtraction. The bit-parallel structure has 100% hardware utilization efficiency. Compared with the existing multiplier-less structures, the proposed structures offer significantly higher throughput rate and involve less area-delay product.


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