alexa High Performance and Low Power VLSI Synchronous System
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

High Performance and Low Power VLSI Synchronous Systems Using an Explicit Pulsed Dual Edge Triggered Flip Flops

R.Ramya1,V.Saranya1 and Y.Vivekananth2
  1. Assistant professor, Department of ECE, K.S.R College of Technology,Tiruchengode, Tamil Nadu, India
  2. Assistant professor, Department of ECE, Bharathiyar Institute of Engineering For Women-Salem, India
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An explicit pulsed dual edge triggered sense amplifier flip flops (DET-FF).In this dual edge triggered sense amplifier flip flop is used for low–power consumption and high performance application. By incorporating the dual edge triggering mechanism, the dual edge triggered flip flop is able to achieve low power consumption that has minimum delay. Clock gating is a popular technique used in many synchronous circuits; hence, the power dissipation is very much reduced. Reducing dynamic power reduction. Clock gating saves power by adding more logic gates in the circuit. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc.


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