alexa Implementation of High Speed Signed Multiplier Using C
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

OMICS International organises 3000+ Global Conferenceseries Events every year across USA, Europe & Asia with support from 1000 more scientific Societies and Publishes 700+ Open Access Journals which contains over 50000 eminent personalities, reputed scientists as editorial board members.

Open Access Journals gaining more Readers and Citations

700 Journals and 15,000,000 Readers Each Journal is getting 25,000+ Readers

This Readership is 10 times more when compared to other Subscription Journals (Source: Google Analytics)

Research Article

Implementation of High Speed Signed Multiplier Using Compressor

D.Srinu1, S.Rambabu2, G.Leenendra Chowdary3
  1. M.Tech, Dept of ECE, SITE, Tadepalligudem, A.P, India
  2. Asst. Professor, Dept of ECE, SITE, Tadepalligudem, A.P, India
  3. Asst. Professor, Dept of ECE, SITE, Tadepalligudem, A.P, India
Related article at Pubmed, Scholar Google
 

Abstract

Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of layout and hence less area for compact VLSI implementation. This work is based on one of the ancient Vedic algorithms (sutras) called Urdhava tiryakbhyam method. These sutras are meant for faster calculation. Though faster when implemented in hardware, it consumes less area. This paper presents a technique to modify the architecture of the Urdhava Tiryakbhyam hardware by using 3_2compressor in order to reduce area and delay to improve overall performance. The coding is done for 16 bit (Q15format), 32 bit (Q31format) and 64 bit (Q63 format) fixed point Q-format by using Verilog HDL and Synthesized by using Xilinx ISE version 9.2i. The performance is compared in terms of area, delay with earlier existing architecture of Urdhava Tiryakbhyam method. The proposed work (compressor based Urdhava Tiryakbhyam method) shows improvements in terms of area and time delay.

Keywords

Share This Page

Additional Info

Loading
Loading Please wait..
Peer Reviewed Journals
 
Make the best use of Scientific Research and information from our 700 + peer reviewed, Open Access Journals
International Conferences 2017-18
 
Meet Inspiring Speakers and Experts at our 3000+ Global Annual Meetings

Contact Us

 
© 2008-2017 OMICS International - Open Access Publisher. Best viewed in Mozilla Firefox | Google Chrome | Above IE 7.0 version
adwords