Implementation of High Speed Signed Multiplier Using Compressor
|D.Srinu1, S.Rambabu2, G.Leenendra Chowdary3
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Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of layout and hence less area for compact VLSI implementation. This work is based on one of the ancient Vedic algorithms (sutras) called Urdhava tiryakbhyam method. These sutras are meant for faster calculation. Though faster when implemented in hardware, it consumes less area. This paper presents a technique to modify the architecture of the Urdhava Tiryakbhyam hardware by using 3_2compressor in order to reduce area and delay to improve overall performance. The coding is done for 16 bit (Q15format), 32 bit (Q31format) and 64 bit (Q63 format) fixed point Q-format by using Verilog HDL and Synthesized by using Xilinx ISE version 9.2i. The performance is compared in terms of area, delay with earlier existing architecture of Urdhava Tiryakbhyam method. The proposed work (compressor based Urdhava Tiryakbhyam method) shows improvements in terms of area and time delay.