alexa Low Power Area-Efficient Adiabatic Vedic Multiplier
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

Low Power Area-Efficient Adiabatic Vedic Multiplier

K.Narendra1 , Sagara Pandu2
  1. PG Student [VLSI DESIGN], Dept. of ECE, G.V.P College of engineering (A), Visakhapatnam, A.P, India
  2. Assistant professor, Dept. of ECE, G.V.P College of engineering (A), Visakhapatnam, A.P, India
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In this paper, we describe adiabatic Vedic multiplier using efficient charge recovery logic (ECRL). Today Power dissipation minimization is the basic principle in making any electronic product portable. Even though there has been a decrease in circuit operating voltages, significant power is lost in switching elements (transistors). With adiabatic logic most of the energy is restored to the source instead of dissipating as heat. Proposed work focuses on the design of low power and area-efficient adiabatic Vedic multiplier using TSMC0.18μm CMOS process technology In Tanner Tool v13.


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