Power and Delay Analysis of Double Edge Triggered D-Flip Flop based Shift Registers in 16nm MOSFET Technology
Flip-Flop is an electronic circuit that stores a logical state of one or more data input signals in response to a clock pulse. During recurring clock intervals to receive and maintain data for a limited time period sufficient for other circuits within a system to further process data. Power dissipation is an important parameter in the design of VLSI circuits, and the clock network is responsible for a substantial part of it (up to 50%). When the supply voltage is decreased the speed of the logic circuits might be diminished due to reduction in effective input voltage to the transistors. The optimal supply voltage for CMOS logic in terms of Energy-Delay-Product (EDP) is close to the threshold voltage of the nMOS transistor Vtn for the actual process, assuming that the threshold voltage of the pMOS transistor Vtp is approximately equal to −Vtn . The famous Moore’s law states that the number of transistors that are to be integrated on a single die gets doubled for every 18 months and which provens that area of the design is also a major concern. Hence in this paper all the three major concerns of VLSI world, the power consumed, speed and area consumption are concentrated.