alexa Power Efficient 3VL Memory Cell Design Using Carbon Na
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

OMICS International organises 3000+ Global Conferenceseries Events every year across USA, Europe & Asia with support from 1000 more scientific Societies and Publishes 700+ Open Access Journals which contains over 50000 eminent personalities, reputed scientists as editorial board members.

Open Access Journals gaining more Readers and Citations

700 Journals and 15,000,000 Readers Each Journal is getting 25,000+ Readers

This Readership is 10 times more when compared to other Subscription Journals (Source: Google Analytics)

Special Issue Article

Power Efficient 3VL Memory Cell Design Using Carbon Nanotube Field Effect Transistors

S.Tamil Selvan, B.PremKumar, G.LAXMANAA
  1. HOD, Dept. of ECE, Sri Krishna Engineering College, Arakonam, TamilNadu, India
  2. Asst. Professor, Dept.of Electronics and Communication Engineering, SMKFIT, Chennai, Tamil Nadu, India
  3. PG Student, Dept. Electronics and Communication Engineering, SMKFIT, Chennai Tamil Nadu, India
Related article at Pubmed, Scholar Google
 

Abstract

This paper presents a design of a 3VL memory cell using carbon nano-tube field-effect transistors (CNTFETs). 3VL is a promising alternative to conventional binary logic, as it has better performance in terms of area, power and also reduces interconnect delay. This cell uses a control gate for the write and read operation to make them separate. Transmission gate is used as control gate in this circuit. The CNTFET used for design has different threshold voltages to achieve ternary logic. This multi threshold voltage is obtained by varying the diameter of the CNT used. Chirality of the CNTFETs is utilized for varying the diameter of the CNT and it also avoids the usage of additional power supplies. The channel length used here is 18nm wide. The power consumption is reduced as there is absence of stand-by power dissipation. Second order effects are removed by using CNTFET in the circuit. The two memory operations, bit read and bit write operation of the proposed ternary cell perform correctly at 0.9V power supply. In a ternary system, it only takes log3 (2n) bits to represent an n-bit binary number. The proposed ternary memory cell achieves a significant saving in area compared with existing design since the λ rules are different for CNTFET. The parameters are measured using HSPICE.

Keywords

Share This Page

Additional Info

Loading
Loading Please wait..
Peer Reviewed Journals
 
Make the best use of Scientific Research and information from our 700 + peer reviewed, Open Access Journals
International Conferences 2017-18
 
Meet Inspiring Speakers and Experts at our 3000+ Global Annual Meetings

Contact Us

 
© 2008-2017 OMICS International - Open Access Publisher. Best viewed in Mozilla Firefox | Google Chrome | Above IE 7.0 version
adwords