alexa Power Optimisation of Scan Based IC Testing
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

Power Optimisation of Scan Based IC Testing

B.BalaBhuvanapriya1, S.Janani1
  1. PG Student [VLSI], Department of ECE, Sri Eshwar College of Engineering, Coimbatore, Tamilnadu, India
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In this paper, the main aim of this project is design the low power VLSI technology. The reason for the power dissipation is switching activity in the circuit. In base paper they used Dual Mode One Latch Double Edge Triggered Scan flop for reducing the switching activity. If switching activity reduces means the power dissipation will also reduce. Scan flop is nothing but combination of D-Flip flop and Multiplexer. The scan flops are combining with shift register to form a scan chain. The scan chains are used to make the testing operation in easy manner. Dual mode one latch double edge triggered is used to reduce the multi cycle path constraints. Due to the reduction of switching activity the power dissipation and time delay will reduce. But this method is older. Nowadays lot of technologies is invented. From that two methods are used. One is Gated logic circuit and Precomputation method. In Gated logic method the AND gate will be use in scan flop for reducing the power effectively. And in precomputation method comparators are used with scan chain.


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