alexa Reduction of Decoding Time in Majority Logic Decoder f
ISSN ONLINE(2320-9801) PRINT (2320-9798)

International Journal of Innovative Research in Computer and Communication Engineering
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Special Issue Article

Reduction of Decoding Time in Majority Logic Decoder for Memory Applications

K.Jayalakshmi1, B.Sivasankari2
  1. PG-Scholar, Electronics and communication, SNS College of technology, Coimbatore, India
  2. Assistant Professor, Electronics and communication, SNS College of technology, Coimbatore, India
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Abstract

An error detection method for EG-LDPC codes with majority logic decoding is presented in this paper. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. They are simple to implement and have modular encoder and decoder. However, they require a large decoding time that impacts memory applications. Mostly memory applications require low latency encoders and decoders. So the proposed method has reduced a decoding time by detecting whether a word has errors in the first iteration of majority logic decoding and when there are no errors in the decoding ends without completing the rest of the iterations. Since most words in a memory will be error free, so the average decoding time is greatly reduced compared to existing methods

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