alexa Test the S27 Benchmark Circuit by Using Built In Self
ISSN ONLINE(2278-8875) PRINT (2320-3765)

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
Open Access

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Research Article

Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

S.Nagaraju1, Ch.N.L.Sujatha2, J.S.S.Ramaraju3
  1. M.Tech ECE Pursuing, Bhimavaram Institute of Engineering & Technology, West Godavari, A.P, India
  2. Assistant Professor, Department of ECE, Bhimavaram Institute of Engineering & Technology, West Godavari, A.P, India
  3. Assistant Professor, Department of ECE, Bhimavaram Institute of Engineering & Technology(BVRM), West Godavari,A.P, India
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In the proposed method we are test the S27 sequential circuit by using Built in Self Test.This paper describes an on-chip test generation method for functional broadside tests. The hardware was base on the application of primary input sequences initial from a well-known reachable state, therefore using the circuit to produce additional reachable states. Random primary enter sequences were changed to avoid repeated synchronization and thus defer varied sets of reachable states. Functional broadside tests are two-pattern scan based tests that avoid over testing by ensuring that a circuit traverses only reachable states in the functional clock cycles of a check. These consist of the input vectors and the equivalent responses. They check for proper operation of a verified design by testing the internal chip nodes. Useful tests cover a very high percentage of modeled faults in logic circuits and their generation is the main topic of this method. Often, functional vectors are understood as verification vectors, these are used to verify whether the hardware actually matches its specification. Though, in the ATE world, any one vectors applied are understood to be functional fault coverage vectors applied during developing test. This paper show the on chip test Generation for a bench mark circuit using simple fixed hardware design with small no of parameters altered in the design for the generation of no of patterns. If the patterns of the input test vector results a fault simulation then circuit test is going to fail.

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