alexa DESIGN OF 32-BIT RISC CPU BASED ON MIPS | Abstract
ISSN: 1948-1432

Journal of Global Research in Computer Sciences
Open Access

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Research Article Open Access

Abstract

The main aim of the project is simulation and synthesis of the 32-bit RISC CPU based on MIPS. The project involves design of a simple RISC processor and simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor .In this work, we analyze MIPS instruction format, instruction data path, decoder module function and design theory based on RISC (Reduced Instruction Set Computer) CPU instruction set. Furthermore, we use pipeline design process to simulate successfully, which involves instruction fetch (IF), instruction decoder (ID), execution (EXE), data memory (MEM), write back (WB) modules of 32-bit CPU based on RISC CPU instruction set. Function of IF module is fetches the instruction from memory. The function of ID stage is sends control commands i.e., instructions are sending to control unit and decoded here. The EXE stage executes arithmetic. Main component of the EXE stage is ALU. The MEM stage is to fetch data from memory and store data to memory, if instruction is not memory/IO instruction, result is sent to WB stage. At last WB stage charges of writing the results, stores data and input data to register file. The purpose of WB stage is to write data to destination register.The idea of this project was to create a RISC processor as a building block in VHDL than later easily can be included in a larger design. It will be useful in systems where a problem is easy to solve in software but hard to solve with control logic. However at a high level of complexity it is easier to implement the function in software. In this project for simulation we use Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification. The language we used here is VHDL, and tools required here are MODELSIM III SE 6.4b – Simulation XILINX-ISE 10.1 – Synthesis. The applications are automatic robot control, bottling plant.

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Author(s): N.Alekya ,P.Ganesh Kumar

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