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Research Article Open Access
This paper demonstrates a CMOS frequency synthesizer design, whose primary purpose is to test the designer’s high speed, mixed-signal CMOS circuit design skill. Line codes are the techniques for representing digital sequences by pulse waveforms suitable for baseband transmission. NRZ or non return to zero is an important Line coding method. NRZ pulses are of full bit duration. We do not get square waveform in conventional current starved VCO. So, the conventional current starved VCO cannot be used for generating NRZ line coding as it is necessary that the output waveform of VCO should be square wave for NRZ coding. This new current starved CMOS VCO is used to design a DPLL. Furthermore, this DPLL design is used to generate a clock for a 8.33Mbits/second with NRZ data format for center frequency at VCO. The DPLL presented here uses XOR phase detector for reducing jitter noise and divide by two stage is used in the feedback loop for frequency synthesis. The DPLL is designed uses active PI filter.