Adder Design Using QCA Technique with Area Delay Efficient
|R.Nithiyanandham1, S.Charles Lekonard 2 ,U.Duraisamy 3 ,V.P.Ahmeed Faheem 4 , V.M Navaneethakrishnan 5
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In this paper, a new 128 bit QCA adder was presented. It achieved the speed performance higher than all the existing adders. It decreases the number of QCA cells compared to previously testimony design. The proposed QCA adder design is based on new algorithm that requires only three majority gates and two inverters for the QCA addition. The area necessity of the QCA adders is comparable cheap with the RCA and CFA established. The novel adder operated in the RCA fashion, but it could propagate a carry signal through a number of cascade MGs significally lower than conventional RCA adders. In addition, because of the adopted basic logic and layout approach, the number of clock cycles required of completing the explanation was limited. As transistor decrease in size more and more of them can be accommodated in on its own die, thus increasing the chip computational capabilities. On the other hand, transistors cannot find much lesser than their existing size. The QCA approach represents one of the probable solutions in overcome this physical limit, even though the design of logic modules in QCA is not forever uncomplicated.